搜索资源列表
CPU
- Xilinx Modelsim下制作的处理器设计以及添加了外部接口处理。-Xilinx Modelsim produced the design of the processor, and add an external interface.
timer
- 计时器的Verilog描述 CPU设计者可以借鉴 -Verilog decription of the timer in processors
cpu16
- 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic u
CPU_Architecture
- Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common netw
cpu_eightbit
- vhdl implementation of an eight bit cpu
uart
- 用ALTERA的芯片做的多串口代码，内部做了3个通用串口，适合51 ARM等CPU，有完整的ALTERA工程和仿真波形-uart FOR ALTERA
S7_PS2_RS232
- 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
VHDL
- 基于VHDL设计的通用实验CPU中译码器部分，用于进行指令译码。-VHDL design of experiments based on general-purpose CPU in the decoder part, used for instruction decoding.
WatchForLab
- This was the first lab assigmnet in the course CPU Architecture, creat a basic watch
VHDLmipsPipeline
- 32 位MIP流水线CPU设计，5 stage，代码详细，包括ALU,存储器,寄存器等，是个很不错的CPU设计-32 MIP pipelined CPU design, 5 stage, the code in detail, including the ALU, memory, registers, etc. is a very good CPU design
CPU16
- 自己用VHDL写的16位的CPU，在学校的课程上通过了测试。-Own use VHDL to write a 16-bit CPU, in school curriculum passed the test.
CPU_16_Beta_1.0
- VHDL CPU 16 16位的简易CPU 开发工具为Xilinx-VHDL CPU 16 a simple CPU in VHDL
ESAM_CARD
- CPU卡程序 已经在电表应用 性能良好 适合国网要求的协议-CPU card procedures have been well-suited to the meter application performance requirements of an agreement State Grid
cpu
- 基于VHDL的单周期cpu开发，网上找的-cpu design
Microprogramcontroller
- 微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
cpu-poc
- 满足并行输出输入的功能，同时与打印机相连，程序中又添加了微处理器的程序。-To meet the parallel input-output function, while with the printer connected to the program has added a microprocessor program.
course-design-cpu-poc
- 满足并行输出输入的功能，同时与打印机相连，程序中又添加了微处理器的程序。-To meet the parallel input-output function, while with the printer connected to the program has added a microprocessor program.